/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
 *  Copyright 2024-2025 NXP
 */

#ifndef __IMX94_POWER_H
#define __IMX94_POWER_H

#define IMX94_PD_ANA		0
#define IMX94_PD_AON		1
#define IMX94_PD_BBSM		2
#define IMX94_PD_M71		3
#define IMX94_PD_CCMSRCGPC	4
#define IMX94_PD_A55C0		5
#define IMX94_PD_A55C1		6
#define IMX94_PD_A55C2		7
#define IMX94_PD_A55C3		8
#define IMX94_PD_A55P		9
#define IMX94_PD_DDR		10
#define IMX94_PD_DISPLAY	11
#define IMX94_PD_M70		12
#define IMX94_PD_HSIO_TOP	13
#define IMX94_PD_HSIO_WAON	14
#define IMX94_PD_NETC		15
#define IMX94_PD_NOC		16
#define IMX94_PD_NPU		17
#define IMX94_PD_WAKEUP		18

#define IMX94_PERF_M33		0
#define IMX94_PERF_M33S		1
#define IMX94_PERF_WAKEUP	2
#define IMX94_PERF_M70		3
#define IMX94_PERF_M71		4
#define IMX94_PERF_DRAM		5
#define IMX94_PERF_HSIO		6
#define IMX94_PERF_NPU		7
#define IMX94_PERF_NOC		8
#define IMX94_PERF_A55		9
#define IMX94_PERF_DISP		10

#endif /* __IMX94_POWER_H */
